Sunday, April 27, 2014

Smart Energy Saving on SAMSUNG Galaxy S5


Samsung galaxy S5 is equipped with a ultra-power saving mode which is a useful for almost all the mobile phone lovers. Nowadays Android based Mobile phones are capable of reducing the power consumption by slowing down the processor and GPU to gain some additional battery life. Sometimes saving the battery life does not make any use since the frequency reduced MPSoC must undergo with the burden and only adds the lagging as well as the user frustration.

Samsung has come with a new idea to make the colors of the display fade (color theme will be gray), restrict the number of applications (cannot run your favorite games) which will result a gain of additional battery life. Once the ultra-power saving mode is activated the user can only make calls, compose text messages, surf web through a primitive browser, record voice etc… One big question you might have is what I can do if I cannot access my Facebook account, twitter account or my favorite game. The idea is to make the battery life longer by shutting down luxury features.

Sunday, April 20, 2014

Correlation Power Analysis (CPA)


Correlation Power Analysis Attacks
Correlation Power Analysis (CPA) is one of the most fable power based side channel analysis attacks. CPA attack was proposed by Brier et. al [1] in 2004 and works well even with noise. Unlike (Differential Power Analysis) DPA, CPA has a high convergence towards the correct hypothesis. CPA uses Pearson correlation coefficient algorithm to correlate the hypothetical power consumption with the data being processed. I have some figures to show in detail explanation of CPA but unpublished work cannot be included to my blog (Oh hell yeah. I am lazy to redraw figures for my papers again).
Pearson Correlation Coefficients can be varied from -1 to +1. Sometimes in the CPA graphs, the secret key behaves as a gradual descend and then a rise. This is because, we are not sure about the polarity of the correlation coefficients and sometimes the correlation coefficients are started from one end (+ve or -ve) and will converge to the other end. The absolute values of the correlation coefficients are plotted and that is the reason for descend-ascend behavior which makes a huge puzzle for researchers who use DPA.  I will post a CPA graph once the research is published.
[1]. Eric Brier, Christophe Clavier, Francis Olivier: Correlation Power Analysis with a Leakage Model. CHES 2004: 16-29

Thursday, April 17, 2014

Power Analysis Attacks on AES

Advanced Encryption Standard is most widely used encryption algorithm in a symmetrical key cryptography. AES was standardized in 2001 after 3 year analysis for vulnerabilities. However the many cryptographic researchers found vulnerabilities of the implementation of AES algorithm and one of the vulnerabilities reported in literature is power analysis. Power analysis attacks exploit the power consumption of the encryption process with the data being processed. Power analysis attacks can be divided to many categories: 1) Simple power analysis; 2) differential power analysis.
Power consumption for logic 0 and logic 1 are clearly distinguishable in the power trace when simple power analysis can be performed. Some simple power analysis attacks involve analyzing one power trace. But often more than one power trace is used in simple power analysis.  Differential power analysis uses statistical methods to identify the correlation between the power dissipation of the device with the data being processed. Differential power analysis, Correlation power analysis and Mutual information analysis are the example for well famous differential power analysis attacks.
Power consumption of a device is the sum of the power consumption of all logic gates. Total power dissipation of a logic gate is the sum of the static and dynamic power consumption of the logic gate. Logic gates are made from CMOS transistors. Explaining the detail of each logic gate is too extensive and only basics are explained. Static power consumption depends on the leakage current of the logic gate and the dynamic power consumption of the logic gate, depends on the state transition of the logic gate.  The table below shows the power consumption for different state transitions.
Traditional power analysis attacks exploit the dynamic power dissipation of the device. That is by correlating the power consumption with the dynamic power consumption, an adversary has the capability to deduce the secret key. Often static power consumption is neglected when compared with dynamic power analysis. When the transistor width is less than 90mn the static power consumption plays a major role in the total power dissipation. Recently a new exploitation in static power dissipation is announced by researchers, where the static power consumption is taken into account.   Power analysis attacks are presented in both microprocessors as well as in circuits.

In order to thwart power analysis attacks, various countermeasures have been proposed by cryptographic researchers. Masking the data being processed, flatten the current drawn by the device and hide the dynamic power using a compliment identical processing unit to obfuscate the power consumption from the data being processed.

Wednesday, April 16, 2014

SASEBO GIII

SASEBO (Side-channel Attack Standard Evaluation Board) is a commercially available product which is developed by AIST Japan. Although the SASEBO has a fable story, the success of the product made the SASEBO to be used among crystallographic researchers in a twinkling. Power analysis attacks are very intrusive and invasive which makes the thwarting a racking task and must be eliminated at the design stage. SASEBO product line helps the cryptography researchers to test the power analysis attacks on their designs and produce side channel resistant products. Below a snap of the latest product by AIST, SASEBO GIII is shown.

This board is equipped with a Virtex Kintex 7 325T FPGA, which is almost 10x larger than the predecessor SASEBO GII. From GII to GIII by the AIST has improved lot of characteristics such as clock speed, voltage regulators and even the price. Unlike SASEBO GII, the GIII runs at 200MHz which allows the user to test designs in more close to the operating clock speeds of vulnerable designs whereas in GII the maximum clock configuration which can be set by the control FPGA is 24MHz. GII has only a very basic voltage regulator but in GIII, 4 regulators were used. Both GII and GIII allow user to power up the device via the USB where lots of Electro Magnetic noise is haunted.  I am not going to talk about the price since it is not mentioned in RIST web site.
Programing GIII is a hectic task which requires mammoth patience. Bit file which contains the compiled design, is ~30MB large and Xilinx platform cable takes abound 15 minutes to program the flash memories which are 128MB large. However being with the state of the art, GIII offers the best experience in power analysis attacks. Few years ago it was an agony to build just the experimental setup without any guarantee about absorbing excitement.   


Thursday, April 3, 2014

Wednesday, April 2, 2014